List of Intel CPU microarchitectures

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The following is a partial list of Intel CPU microarchitectures. The list is incomplete. Additional details can be found in Intel's Tick-Tock model.

x86 microarchitectures

Year Microarchitecture Pipeline stages max. Clock
1989 486 (80486) 3 100 MHz
1993 P5 (Pentium) 5 300 MHz
1995 P6 (Pentium II) 14 (17 with load & store/retire)[further explanation needed] 450 MHz
1999 P6 (Pentium III) 12 (15 with load & store/retire) 450~1400 MHz
2000 NetBurst (Pentium 4) 20 unified with branch prediction 800~3466 MHz
2003 Pentium M 10 (12 with fetch/retire)[further explanation needed] 400~2133 MHz
2004 Prescott 31 unified with branch prediction 4000 MHz
2006 Intel Core 12 (14 with fetch/retire) 3333 MHz
2008 Nehalem 20 unified (14 without miss prediction) 3600 MHz
2008 Bonnell 16 (20 with prediction miss) 2100 MHz
2011 Sandy Bridge 14 (16 with fetch/retire) 4000 MHz
2013 Silvermont 14-17 (16-19 with fetch/retire) 2670 MHz
2013 Haswell 14 (16 with fetch/retire) 4400 MHz
2015 Skylake 14 (16 with fetch/retire) 4200 MHz
2016 Goldmont (Atom microarchitecture) 20 unified with branch prediction 3500 MHz
2016 Kabylake 14 (16 with fetch/retire) 4500 MHz
2017 Cannonlake 14  ?
  • pre-P5:
    • 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80.
    • 186: included a DMA controller, interrupt controller, timers, and chip select logic.
    • 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086.
    • i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since.
    • i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining.
  • P5: original Pentium microprocessors, first x86 processor with super scaling feature, branch prediction and RISC μop decode scheme.
  • P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, integrated register renaming and Out of Order execution.
  • NetBurst: Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache.
  • Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
  • Intel Core: reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion&enhanced micro-op fusion with wider front end and decoder, larger Out of Order core and renamed register, support loop stream detector and large shadow register file.
    • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, and SSE4.1 instructions, support xop and F/SAVE&F/STORE instruction and enhance register alias table and larger integer register file.
  • Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die.
    • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
  • Bonnell: 45 nm, low-power, in-order microarchitecture for use in Atom processors.
    • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
  • Larrabee (cancelled 2010): multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).
  • Sandy Bridge: released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.[1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
    • Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.
  • Silvermont: 22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
    • Airmont: 14 nm shrink of the Silvermont microarchitecture.
  • Haswell: 22 nm microarchitecture, released June 3, 2013.
    • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
  • Skylake: new 14 nm microarchitecture, released August 5, 2015.
    • Goldmont: 14 nm Atom microarchitecture, borrows heavily from Skylake processors, released April 2016.[2][3]
    • Kaby Lake: successor to Skylake, broke Intel's Tick-Tock schedule due to delays with the 10 nm process.
    • Cannonlake: expected in late 2017. It will be a 10 nm shrink of Kaby Lake. Formerly called Skymont.
  • Ice Lake: new 10 nm microarchitecture, expected in 2018.
    • Tiger Lake: an update of Ice Lake, serving as "semi-Tock" of the Intel's Tick-Tock strategy, expected in 2019.

Itanium microarchitectures

Roadmap

Archi­tectural change Fabri­cation process Micro­archi­tecture Code­names Release date Processors
8P/4P Server 4P/2P Server/WS Enthusiast/​WS Desktop Mobile
Tick (New fabri­cation process) 65 nm P6, NetBurst Presler, Cedar Mill, Yonah 2006-01-05 Presler Cedar Mill Yonah
Tock (New micro­archi­tecture) Core Merom[5] 2006-07-27[6] Tigerton Woodcrest
Clovertown		 Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11[7] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 2008-11-17[8] Beckton Gainestown Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 2010-01-04[9][10] Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Tock Sandy Bridge Sandy Bridge (2nd Gen) 2011-01-09[11] (None)[12] Sandy Bridge-EP Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm[13] Ivy Bridge (3rd Gen) 2012-04-29 Ivy Bridge-EX[14] Ivy Bridge-EP[14] Ivy Bridge-E[15] Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell (4th Gen) 2013-06-02 Haswell-EX Haswell-EP Haswell-E Haswell-DT[16]
  • Haswell-MB (37 - 57W TDP, PGA package)
  • Haswell-H (47W TDP, BGA package)
  • Haswell-ULP/ULX (11.5W - 15W TDP)[16]
Optimizations (Fabrication process/microarchitecture improvements) Devil's Canyon[17] 2014-06 (None) (None) (None) Haswell-DT (None)
Tick 14 nm[13] Broadwell (5th Gen)[18] 2014-09-05 Broadwell-EX [19] Broadwell-EP [19] Broadwell-E Broadwell-DT Broadwell-H (37W - 47W TDP)

Broadwell-U (15W - 28W TDP)

Broadwell-Y (4.5W TDP)
Tock Skylake[18] Skylake (6th Gen)[18] 2015-08-05[20] Skylake-EX Skylake-SP (formerly Skylake-EP) [21] Skylake-X [22] Skylake-S Skylake-H (35W - 45W TDP)

Skylake-U (15W - 28W TDP)

Skylake-Y (4.5W TDP)
Optimizations[23][24][25][26] Kaby Lake (7th Gen)[27] 2017-01-03[28] Kaby Lake-X [29] Kaby Lake-S Kaby Lake-H (35W - 45W TDP)

Kaby Lake-U (15W - 28W TDP)

Kaby Lake-Y (4.5W TDP)
Coffee Lake 1H 2018[30]
Process 10 nm[31] Cannonlake 2H 2017[27]
Architecture Ice Lake[26] Ice Lake[32] 2018
Optimization[26] Tigerlake[26] 2019
Process 7 nm[31]
Architecture
Optimization
Process 5 nm[31]
Architecture
Optimization

Atom Roadmap[33]
Fabrication process Microarchitecture Release date Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server Communication CE
Tick 45 nm Bonnell 2008 Silverthorne N/A Diamondville Tunnel Creek & Stellarton N/A Sodaville
Tock 2010 Lincroft Pineview Groveland
Tick 32 nm Saltwell 2011 Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview) Clover Trail (Cloverview) Cedar Trail (Cedarview) Unknown Centerton & Briarwood Unknown Berryville
Tick 22 nm Silvermont 2013 Merrifield (Tangier) [34] & Moorefield (Anniedale)[35] & Slayton Bay Trail-T (Valleyview) Bay Trail-M (Valleyview) Bay Trail-D (Valleyview) Bay Trail-I (Valleyview) Avoton Rangeley Unknown
Tick 14 nm[33] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview) [36] Braswell [37] Denverton Cancelled cross.svg Cancelled Unknown Unknown
Tock Goldmont[38] 2016 Broxton Cancelled cross.svg Cancelled Willow Trail Cancelled cross.svg Cancelled
Apollo Lake		 Apollo Lake [39] Denverton [40] Unknown Unknown
Optimization Unknown 2017 Unknown Unknown Gemini Lake Unknown Unknown Unknown
Process 10 nm Unknown 2018 Unknown Unknown Mercury Lake Unknown Unknown Unknown

See also

References

  1. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  2. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  3. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  4. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  5. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  6. ↑ Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing, Intel Unveils World's Best Processor
  7. ↑ Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology
  8. ↑ Intel Launches Fastest Processor on the Planet
  9. ↑ http://download.intel.com/pressroom/kits/32nm/westmere/Mark_Bohr_32nm.pdf
  10. ↑ Revolutionizing How We Use Technology—Today and Beyond
  11. ↑ Intel Sandy Bridge chip coming January 5
  12. ↑ Intel Ivy Bridge CPU Range Complete by Next Year
  13. ↑ 13.0 13.1 22nm technology. May 2011
  14. ↑ 14.0 14.1 http://vr-zone.com/articles/ivy-bridge-ep-and-ex-coming-up-in-a-year-s-time--the-multi-socket-platform-heaven/15488.html
  15. ↑ Ivy Bridge-E Delayed Until Second Half of 2013
  16. ↑ 16.0 16.1 Lua error in package.lua at line 80: module 'strict' not found.
  17. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  18. ↑ 18.0 18.1 18.2 After Intel's Haswell comes Broadwell - SemiAccurate
  19. ↑ 19.0 19.1 Intel to release 22-core Xeon E5 v4 "Broadwell-EP" late in 2015
  20. ↑ The wait for Skylake is almost over, first desktop chips likely to hit August 5
  21. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  22. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  23. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  24. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  25. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  26. ↑ 26.0 26.1 26.2 26.3 Lua error in package.lua at line 80: module 'strict' not found.
  27. ↑ 27.0 27.1 Lua error in package.lua at line 80: module 'strict' not found.
  28. ↑ http://arstechnica.com/gadgets/2017/01/intel-pushes-out-the-rest-of-its-kaby-lake-processors-for-2017s-pcs/
  29. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  30. ↑ http://wccftech.com/intel-14nm-coffee-lake-10nm-cannonlake-2018/
  31. ↑ 31.0 31.1 31.2 Lua error in package.lua at line 80: module 'strict' not found.
  32. ↑ http://www.fool.com/investing/general/2016/01/18/what-is-the-name-of-intels-third-10-nanometer-chip.aspx
  33. ↑ 33.0 33.1 Lua error in package.lua at line 80: module 'strict' not found.
  34. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  35. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  36. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  37. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  38. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  39. ↑ Lua error in package.lua at line 80: module 'strict' not found.
  40. ↑ Lua error in package.lua at line 80: module 'strict' not found.

External links

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