Intel MCS-51

Intel P8051 microcontroller.

SAB-C515-LN by Infineon is based on the 8051

The Intel MCS-51 (commonly termed 8051) is a Harvard architecture, complex instruction set computing (CISC) instruction set, single chip microcontroller (µC) series developed by Intel in 1980 for use in embedded systems. Intel's original versions were popular in the 1980s and early 1990s and enhanced binary compatible derivatives remain popular today.

Intel's original MCS-51 family was developed using N-type metal-oxide-semiconductor (NMOS) technology, but later versions, identified by a letter C in their name (e.g., 80C51) used complementary metal–oxide–semiconductor (CMOS) technology and consume less power than their NMOS predecessors. This made them more suitable for battery-powered devices.

The family was continued in 1996 with the enhanced 8-bit MCS-151 and the 8/16/32-bit MCS-251 family of binary compatible microcontrollers. While Intel no longer manufactures the MCS-51, MCS-151 and MCS-251 family, enhanced binary compatible derivatives made by numerous vendors remain popular today. Some derivatives integrate a digital signal processor (DSP). Beyond these physical devices, several companies also offer MCS-51 derivatives as IP cores for use in field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC) designs.

Important features and applications

i8051 microarchitecture

The 8051 architecture provides many functions (central processing unit (CPU), random access memory (RAM), read-only memory (ROM), input/output (I/O), interrupt logic, timer, etc.) in one package:

• 8-bit arithmetic logic unit (ALU) and accumulator, 8-bit registers (one 16-bit register with special move instructions), 8-bit data bus and 2×16-bit address bus/program counter/data pointer and related 8/11/16-bit operations; hence it is mainly an 8-bit microcontroller
• Boolean processor with 17 instructions, 1-bit accumulator, 32 registers (4 bit-addressable 8-bit) and up to 144 special 1 bit-addressable RAM variables (18 bit-addressable 8-bit)
• Multiply, divide and compare instructions
• 4 fast switchable register banks with 8 registers each (memory mapped)
• Fast interrupt with optional register bank switching
• Interrupts and threads with selectable priority
• Dual 16-bit address bus – It can access 2 x 2¹⁶ memory locations – 64 KB (65,536 locations) each of RAM and ROM
• 128 bytes of on-chip RAM (IRAM)
• 4 KiB of on-chip ROM, with a 16-bit (64 KiB) address space (PMEM). Not included on 803X variants
• Four 8-bit bi-directional input/output port
• UART (serial port)
• Two 16-bit Counter/timers
• Power saving mode (on some derivatives)

One feature of the 8051 core is the inclusion of a boolean processing engine which allows bit-level boolean logic operations to be carried out directly and efficiently on select internal registers and select RAM locations. This feature helped cement the 8051's popularity in industrial control applications because it reduced code size by as much as 30%. Another feature is the inclusion of four bank selectable working register sets which greatly reduce the amount of time required to complete an interrupt service routine. With one instruction, the 8051 can switch register banks versus the time consuming task of transferring the critical registers to the stack, or designated RAM locations. These registers also allowed the 8051 to quickly perform a context switch.

Once a UART, and a timer if necessary, has been configured, the programmer needs only write a simple interrupt routine to refill the send shift register whenever the last bit is shifted out by the UART and/or empty the full receive shift register (copy the data somewhere else). The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks.

Derivate features

As of 2013, new derivates are still developed by many major chipmakers, and major compiler suppliers such as IAR Systems, Keil and Altium Tasking continuously release updates.

MCS-51 based microcontrollers typically include one or two UARTs, two or three timers, 128 or 256 bytes of internal data RAM (16 bytes of which are bit-addressable), up to 128 bytes of I/O, 512 bytes to 64 KB of internal program memory, and sometimes a quantity of extended data RAM (ERAM) located in the external data space. The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine cycle, and have clock frequencies of up to 100 MHz, and are thus capable of an even greater number of instructions per second. All Silicon Labs, some Dallas and a few Atmel devices have single cycle cores.

8051 variants may include built-in reset timers with brown-out detection, on-chip oscillators, self-programmable Flash ROM program memory, built-in external RAM, extra internal program storage, bootloader code in ROM, EEPROM non-volatile data storage, I²C, SPI, and USB host interfaces, CAN or LIN bus, ZigBee or Bluetooth radio modules, PWM generators, analog comparators, A/D and D/A converters, RTCs, extra counters and timers, in-circuit debugging facilities, more interrupt sources, extra power saving modes, etc.

In many engineering schools the 8051 microcontroller is used in introductory microcontroller courses.

Memory architecture

The MCS-51 has four distinct types of memory – internal RAM, special function registers, program memory, and external data memory.

The 8051 is designed as a strict Harvard architecture; it can only execute code fetched from program memory, and has no instructions to write to program memory.

Most 8051 systems respect this distinction, and so are unable to download and directly execute new programs. The strict Harvard architecture has the advantage of making such systems immune to most forms of malware. Some 8051 systems have (or can be modified to have) some "dual-mapped" RAM, making them act somewhat more like von Neumann architecture. This (partial) von Neumann architecture has the advantage of making it possible for a Forth boot loader running on the 8051 to write new native code to RAM and then execute it, leading to faster incremental and interactive programming cycles than strict Harvard systems.

Internal RAM

Internal RAM (IRAM) has an 8-bit address space, allowed addresses 0 through 0xFF. IRAM from 0x00 to 0x7F can be accessed directly. The 8052 added IRAM from 0x80 to 0xFF, which must be accessed indirectly; the address is loaded into R0 or R1, and the memory is accessed using the @R0 or @R1 syntax. Most 8051 clones also have a full 256 bytes of IRAM.

The 32 bytes from 0x00–0x1F memory-map the 8 registers R0–R7. 8 bytes are used at a time; 2 program status word bits select between four possible banks,

The 16 bytes (128 bits) at IRAM locations 0x20–0x2F are bit-addressable.

Special function registers

Special function registers (SFR) are located in the same address space as IRAM, at addresses 0x80 to 0xFF, and are accessed directly using the same instructions as for the lower half of IRAM. They can not be accessed indirectly via @R0 or @R1; indirect access to those addresses will access the second half of IRAM.

16 of the SFRs (those whose addresses are multiples of 8) are also bit-addressable.

Program memory

Program memory (PMEM, though less common in usage than IRAM and XRAM) is up to 64 KiB of read-only memory, starting at address 0 in a separate address space. It may be on- or off-chip, depending on the particular model of chip being used. Program memory is read-only, though some variants of the 8051 use on-chip flash memory and provide a method of re-programming the memory in-system or in-application. In addition to code, it is possible to store read-only data in program memory, accessed by the MOVC A, @DPTR instruction. Data is fetched from the address specified in the 16-bit special function register DPTR.

Special jump and call instructions make access within the same 2 KiB of program memory slightly smaller.

External data memory

External data memory (XRAM) is a third address space, also starting at address 0, and allowing 16 bits of address space. It can also be on- or off-chip; what makes it "external" is that it must be accessed using the MOVX (Move eXternal) instruction. Many variants of the 8051 include the standard 256 bytes of IRAM plus a few KB of XRAM on the chip.

The first 256 bytes of XRAM may be accesses using the MOVX A,@R0, MOVX A,@R1, MOVX @R0, A, and MOVX @R1, A instructions. The full 64K may be accessed using MOVX A,@DPTR and MOVX @DPTR,A.

Registers

The only register on an 8051 that is not memory-mapped is the 16-bit program counter PC. This specifies the address of the next instruction to execute. Relative branch instructions supply an 8-bit signed offset which is added to the PC.

8 general-purpose registers R0–R7 may be accessed with instructions 1 byte shorter than others. They are mapped to IRAM between 0x00 and 0x1F. Only 8 bytes of that range are used at any given time, determined by the two bank select bits in the PSW.

The following is a partial list of the 8051's registers, which are memory-mapped into the special function register space:

• (0x81) Stack pointer SP. This is an 8-bit register used by subroutine call and return instructions. The stack grows upward; the SP is incremented before pushing, and decremented after popping a value.
• (0x82–83) Data pointer DP. This is a 16-bit register that is used for accessing PMEM and XRAM.
• (0xD0) Program status word PSW. This contains important status flags:
  • PSW.0: P Parity. Gives the parity (modulo-2 sum of the bits of) the accumulator, A.
  • PSW.1: UD User Defined. For general software use, not otherwise used by hardware.
  • PSW.2: OV Overflow flag. Set when addition produces a signed overflow.
  • PSW.3: RS0 Register select 0. The low-order bit of the register bank. Set when banks at 0x08 or 0x18 are in use.
  • PSW.4: RS1 Register select 1. The high-order bit of the register bank. Set when banks at 0x10 or 0x18 are in use.
  • PSW.5: F0 Flag 0. For general software use, not otherwise used by hardware.
  • PSW.6: AC auxiliary carry. Set when addition produces a carry from bit 3 to bit 4.
  • PSW.7: C Carry bit. Often used as the general register for bit computations, or the "boolean accumulator".
• (0xE0) accumulator A. This register is used by most instructions.
• (0xF0) B register. This is used as an extension to the accumulator for multiply and divide instructions.

256 single bits are directly addressable. These are the 16 IRAM locations from 0x20–0x2F, and the 16 special function registers 0x80, 0x88, 0x90, …, 0xF8. Any bit of these bytes may be directly accessed by a variety of logical operations and conditional branches.

Note that the PSW does not contain the common N (negative) and Z (zero) flags. Instead, because the accumulator is a bit-addressible SFR, it is possible to branch on its most significant bit directly. There is also an instruction to jump if the accumulator is zero or non-zero. There is also a "compare and jump" operation that takes two operands.

Instruction set

Instructions are all 1 to 3 bytes long, consisting of an initial opcode byte, followed by up to 2 bytes of operands.

3/4 of the opcode bytes are assigned to 16 basic ALU instructions. One operand is flexible, while the second (if any) is specified by the operation: the accumulator, an immediate constant, or a RAM address. The most significant nibble of the opcode byte specifies the operation, and the least significant nibble specifies one of the following 12 addressing modes for the flexible operand:

• x8–xF: Register direct, R0–R7
• x6–x7: Register indirect, @R0 or @R1
• x5: Memory direct, a following byte specifies an IRAM or SFR location
• x4: Immediate, a following byte specifies an 8-bit constant. In some cases where an immediate operand is nonsensical, the accumulator is used.

The operations is as follows. Not all support all addressing modes; the immediate mode in particular is unavailable if the flexible operand is written to. Instruction mnemonics use destination, source operand order.

• 0y: INC operand: Increment the specified operand. Opcode 04 specifies "INC A"
• 1y: DEC operand: Decrement the specified operand. Opcode 14 specifies "DEC A"
• 2y: ADD A,operand: Add the operand to the accumulator A.
• 3y: ADDC A,operand: Add the operand, plus the C bit, to the accumulator.
• 4y: ORL A,operand: Logical OR the operand into the A register.
• 5y: ANL A,operand: Logical AND the operand into the A register.
• 6y: XRL A,operand: Logical exclusive-OR the operand into the A register.
• 7y: MOV operand,#data: Move immediate data to the operand. Opcode 74 specifies "MOV A,#data.
• 8y: MOV address,operand: Move data to an IRAM or SFR register.
• 9y: SUBB A,operand: Subtract the operand from the accumulator, with borrow. Note there is no subtract without borrow.
• Ay: MOV operand,address: Move data from an IRAM or SFR register. Opcodes A4 and A5 are not used.
• By: CJNE operand,#data,offset: Compare operand to the immediate data, and branch to PC+offset if not equal. Opcodes B4 and B5 perform CJNE A,operand,offset, for memory direct and immediate operands. Note there is no "compare and jump if equal" instruction.
• Cy: XCH A,operand: Exchange (swap) the accumulator and the operand. Opcode C4 is not used.
• Dy: DJNZ operand,offset: Decrement the operand, and branch to PC+offset if the result is non-zero. Opcodes D4, D6, and D7 are not used.
• Ey: MOV A,operand: Move operand to the accumulator. Opcode E4 is not used. (Use opcode 74 instead.)
• Fy: MOV operand,A: Move accumulator to the operand. Opcode F4 is not used.

Only the ADD, ADDC and SUBB instructions set PSW flags. The INC, DEC, and logical instructions do not. The CJNE instructions modify the C bit only, to the borrow that results from operand1−operand2.

The 64 opcodes x0–x3, plus the few opcodes not used in the above range, are used for other instructions with more limited operand-specification capabilities:

8051/8052 irregular instructions

Opcode	x0	x1	x2	x3	x4
0y	NOP	AJMP page0	LJMP addr16	RR A (rotate right)	INC A
1y	JBC bit,offset	ACALL page0	LCALL addr16	RRC A	DEC A
2y	JB bit,offset	AJMP page1	RET	RL A (rotate left)	(ADD A,#data)
3y	JNB bit,offset	ACALL page1	RETI	RLC A	(ADDC A,#data)
4y	JC offset	AJMP page2	ORL address,A	ORL address,#data	(ORL A,#data)
5y	JNC offset	ACALL page2	ANL address,A	ANL address,#data	(ANL A,#data)
6y	JZ offset	AJMP page3	XRL address,A	XRL address,#data	(XRL A,#data)
7y	JNZ offset	ACALL page3	ORL C,bit	JMP @A+DPTR	MOV A,#data
8y	SJMP offset	AJMP page4	ANL C,bit	MOVC A,@A+PC	DIV AB
9y	MOV DPTR, #imm16	ACALL page4	MOV bit,C	MOVC A,@A+DPTR	(SUBB A,#data)
Ay	ORL C,/bit	AJMP page5	MOV C,bit	INC DPTR	MUL AB
By	ANL C,/bit	ACALL page5	CPL bit	CPL C	CJNE A,#data,offset
Cy	PUSH address	AJMP page6	CLR bit	CLR C	SWAP A
Dy	POP address	ACALL page6	SETB bit	SETB C	DA A (decimal adjust)
Ey	MOVX A,@DPTR	AJMP page7	MOVX A,@R0	MOVX A,@R1	CLR A
Fy	MOVX @DPTR,A	ACALL page7	MOVX @R0,A	MOVX @R1,A	CPL A
	A5	B5	D6	D7
Other	(unused)	CJNE A,address,offset	XCHD A,@R0	XCHD A,@R1

One of the reasons for the 8051's popularity is its range of operations on single bits. Bits are always specified by absolute addresses; there is no register-indirect or indexed addressing. Instructions that operate on single bits are:

• SETB bit, CLR bit, CPL bit: Set, clear, or complement the specified bit
• JB bit,offset: Jump if bit set
• JNB bit,offset: Jump if bit clear
• JBC bit,offset: Jump if bit set, and clear bit
• MOV C,bit, MOV bit,C: Move the specified bit to the carry bit, or vice versa
• ORL C,bit, ORL C,/bit: OR the bit (or its complement) to the carry bit
• ANL C,bit, ANL C,/bit: AND the bit (or its complement) to the carry bit

Although most instructions require that one operand is the accumulator or an immediate constant, it is possible to perform a MOV directly between two internal RAM locations.

Programming

There are various high-level programming language compilers for the 8051. Several C compilers are available for the 8051, most of which allow the programmer to specify where each variable should be stored in its six types of memory, and provide access to 8051 specific hardware features such as the multiple register banks and bit manipulation instructions. There are many commercial C compilers. Small Device C Compiler (SDCC) is a popular open source C compiler. Other high level languages such as C++, Forth, BASIC, Object Pascal, Pascal, PL/M and Modula-2 are available for the 8051, but they are less widely used than C and assembly.

Because IRAM, XRAM, and PMEM (read only) all have an address 0, C compilers for the 8051 architecture provide compiler-specific pragmas or other extensions to indicate where a particular piece of data should be stored (i.e. constants in PMEM or variables needing fast access in IRAM). Since data could be in one of three memory spaces, a mechanism is usually provided to allow determining to which memory a pointer refers, either by constraining the pointer type to include the memory space, or by storing metadata with the pointer.

Related processors

Intel 8031 processors

The 8051's predecessor, the 8048, was used in the keyboard of the first IBM PC, where it converted keypresses into the serial data stream which is sent to the main unit of the computer. The 8048 and derivatives are still used today for basic model keyboards.

The 8031 was a cut down version of the original Intel 8051 that had no internal program memory (read-only memory (ROM)). To use this chip, external ROM had to be added containing the program that the 8031 would fetch and execute. An 8051 chip could be sold as a ROM-less 8031, as the 8051's internal ROM is disabled by the normal state of the EA pin in an 8031-based design. A vendor might sell an 8051 as an 8031 for any number of reasons, such as faulty code in the 8051's ROM, or simply an oversupply of 8051s and undersupply of 8031s.

The 8052 was an enhanced version of the original 8051 that featured 256 bytes of internal RAM instead of 128 bytes, 8 KB of ROM instead of 4 KB, and a third 16-bit timer. The 8032 had these same features except for the internal ROM program memory. Most modern 8051-compatible microcontrollers include these features.

Intel discontinued its MCS-51 product line in March 2007; however, there are plenty of enhanced 8051 products or silicon intellectual property added regularly from other vendors.

The 80C537 and 80C517 are CMOS versions, designed for the automotive industry. Enhancements mostly include new peripheral features and expanded arithmetic instructions. The 80C517 has fail-safe mechanisms, analog signal processing facilities and timer capabilities and 8 KB on-chip program memory. Other features include:

• 256 byte on-chip RAM
• 256 directly addressable bits
• External program and data memory expandable up to 64 KB
• 8-bit A/D converter with 12 multiplexed inputs
• Arithmetic unit can make division, multiplication, shift and normalize operations
• Eight data pointers instead of one for indirect addressing of program and external data memory
• Extended watchdog facilities
• Nine ports
• Two full-duplex serial interfaces with own baud rate generators
• Four priority level interrupt systems, 14 interrupt vectors
• Three power saving modes

Derivate vendors

Current vendors of MCS-51 compatible processors include more than 20 independent manufacturers including Atmel, Infineon Technologies (formerly Siemens AG), Maxim Integrated Products (via its Dallas Semiconductor subsidiary), NXP (formerly Philips Semiconductor), Microchip Technology, Nuvoton (formerly Winbond), ST Microelectronics, Silicon Laboratories (formerly Cygnal), Texas Instruments, Ramtron International, Silicon Storage Technology, Cypress Semiconductor and Analog Devices.

ICs or IPs compatible with the MCS-51 have been developed by:

3

Use as intellectual property

Today, 8051s are still available as discrete parts, but they are mostly used as silicon intellectual property cores. Available in high-level language source code (VHDL or Verilog) or FPGA netlist forms, these cores are typically integrated within embedded systems, in products ranging from USB flash drives to washing machines to complex wireless communication systems on a chip. Designers use 8051 silicon IP cores, because of the smaller size, and lower power, compared to 32 bit processors like ARM Cortex-M series, MIPS and BA22.

Modern 8051 cores are faster than earlier packaged versions. Design improvements have increased 8051 performance while retaining compatibility with the original MCS 51 instruction set. The original Intel 8051 ran at 12 clock cycles per machine cycle, and most instructions executed in one or two machine cycles. A typical maximum clock frequency of 12 MHz meant these old 8051s could execute one million single-cycle instructions, or 500,000 two-cycle instructions, per second. In contrast, enhanced 8051 silicon IP cores now run at one clock cycle per machine cycle, and have clock frequencies of up to 450 MHz. That means an 8051-compatible processor can now execute 450 million instructions per second.

MCU based on 8051

• Atmel: AT89C51, AT89S51, AT83C5134
• Infineon: XC800
• Mentor Graphics: M8051ew
• NXP: NXP700 and NXP900 series
• Silicon Labs: C8051 series
• Texas Instruments CC111x, CC24xx and CC25xx families of RF SoCs

Digital signal processor (DSP) variants

Several variants with an additional 16-bit digital signal processor (DSP) (for example for MP3 or OGG coding/decoding) with up to 675 million instructions per second (MIPS) and integrated USB 2.0 interface or as intellectual property exist.

Enhanced 8-bit binary compatible microcontroller: MCS-151 family

1996 Intel announced the MCS-151 family, an up to 6 times faster variant. 8051 fully binary and instruction set compatible, but with pipelined CPU, 16 bit internal code bus and 6x speed. The MCS-151 family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants.

8/16/32-bit binary compatible microcontroller: MCS-251 family

The 80251 8/16/32-bit microcontroller with 16 MB (24-bit) address-space and 6 times faster instruction cycle was introduced by Intel in 1996. It can perform as an 8-bit 8051, has 24-bit external address space which is 16-bit wide segmented and 32-bit ALU with mostly 8/16/32-bit wide data instructions (also Boolean processor with special registers/memory) and a large CISC instruction set, 40 8/16/32-bit registers with 8 8-bit registers in 4 times fast switching memory banks (maximum 512 addressable 8-bit special registers).

It features extended instructions – see also the programmer's guide – and later variants with higher performance, also available as intellectual property (IP). It is 3-stage pipelined. The MCS-251 family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants from many manufacturers.

See also

• SDK-51 System Design Kit
• DS80C390

Further reading

Books

Intel

• MCS-51 Microcontroller Family User's Manual; Intel; 1994; publication number 121517.
• MCS-51 Macro Assembler User's Guide; Intel; publication number 9800937.
• 8-Bit Embedded Controllers; Intel; 1991; publication number 270645-003.
• Microcontroller Handbook; Intel; 1984; publication number 210918-002.
• 8051 Microcontroller Preliminary Architectural Specification and Functional Description; Intel; 44 pages; 1980.

External links

• Complete tutorial for 8051 microcontrollers
• Instruction set of 8051 microcontroller
• the source website for tutorials and simulator for 8051
• Basic 8051 Interfacing Circuits
• Open source VHDL 8051 implementation (Oregano Systems)

This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.